As is well known, integrated circuits or microcontroller chips are designed in custom configurations for a final user's own requirements. Thus, a problem arises that the assembly process of the individual chip must be optimized to yield a finished product which best suits a specific application of interest to the final user, thereby doing away with rendundant subsystems.
For this purpose, an individual chip is obtained from families of modular systems which can be likened to libraries of components comprising sets of macrocells adapted to perform certain basic functions. By assembling an appropriate and suitable number of macrocells selected from the same family, a single on-chip integrated system can be provided. The final user is then able to use the chip for developing an application of interest, from both the hardware and software viewpoints. Unfortunately, the delivery time for a custom-finished chip to the final user is rather long, e.g., several months.
This has prompted a demand for a need to emulate the chip, particularly the operation of the microcontroller therein, so that the final user can start developing his own application and carry on the development work in parallel with the physical making of the integrated device. Thus, there is a need to provide an emulation chip that closely resembles the system which is to be integrated on the chip product for ultimate delivery to the final user.
The emulation chip is, therefore, an integrated circuit which contains the core, all the peripheral devices, and all the gates available to a family of macrocells for microcontrollers. Each peripheral device can be activated or inactivated to make the microcontroller configuration of the emulation chip similar to that of the microcontroller of the final chip. This is provided by selecting certain gates and peripheral devices from all those available.
Thus, it is a matter of providing an emulation chip with programmable physical and logical connections, specifically between functional modules and interfacing gates. For this purpose, programmable devices must be provided in the emulation chip which can establish all possible connections between chip components. In particular, a system for interconnecting the peripheral devices is required which can handle their interrupt requests simultaneously.
A prior approach to this problem has been to use daisy chain connections which allow one signal to be shared with priority arbitration. In particular, the signal to be arbitrated is an interrupt signal. For this purpose, the CPU is connected to the peripheral devices directly by means of an interrupt line. The interrupt line carries an enable signal which is generated by the CPU to indicate that the CPU is ready for an interrupt to be delivered to a peripheral device. A connection matrix of the daisy chain type is a hardware device which can arbitrate the priority schedule for the various peripheral devices. However, this known approach cannot be applied to an emulation chip, wherein the priority schedule for the peripheral devices cannot be known in advance, but is to be decided upon by the final user.
There is a need to provide a peripheral connecting device which has structural and functional features so as to allow the arbitration of signals, specifically interrupt signals from the peripheral devices to the CPU, to be programmed. Another need is to provide a connection device with priority arbitration for chip emulating circuits operating at a comparable speed to that of the chip being emulated.